ECE463/563 – Microprocessor Architecture Project #3Microprocessor Architecture1代写 The goal of this project is to design and implement a cache simulator (level-1 cache only).The project3_code.tar.gz archive Due date: May 3, 2019Objective Microprocessor Architecture1代写The goal of this project is to design and implement a cache simulator (level-1 cache only).Microprocessor Architecture1代写Code organizationThe project3_code.tar.gz archive contains the C++ code templates for the simulator, as well as test cases to validate its operation.In order to extract the code in a Linux environment, you can invoke the following command:tar –xzvf project3_code.tar.gzThis will create a project3_code folder containing the following:h/cache.cc: code templates for the cache simulator. These are the only files that you need to modify to implement thesimulator.Microprocessor Architecture1代写testcases: test cases to validate the operation of the L1 cache simulator. This folder contains six test cases (testcase0-5). For each of them, you will find two files: cc and testcaseN.out. The former contains the test case implementation, and the latter the expected output of the test case. You should not modify any of the test casefiles.Makefile:Makefile to be used to compile the  The use of this Makefile will cause an object file (.o) to be created for each C++ file that is part of the project. If the compilation succeeds, the binaries corresponding to the test cases will be generated in the bin folder. You don’t need to modify the Makefile.traces: memory access traces used by the test cases. t is a short synthetic trace to help you debugyour code (and is used in testcase0). GCC.t, MCF.t and LBM.t are significantly longer memory access traces from real applications from the SPEC2006 benchmark suite (https://www.spec.org/cpu2006/), and they are used in testcase1-5.bin: once you compile the code, the test case binaries will be saved into this folder.Important Microprocessor Architecture1代写The cache.h header file is commented and contains details on the functions/methods that you need to implement. Be sure to read the comments in this header file before you start coding.Assumptions RequirementsThe tool should allow simulating an L1 cache with configurable capacity, cache line size, associativity, write hit and write miss policies, hit time and miss penalty. In addition, the width of the memory addresses should also be configurable. All these parameters can be set through the cacheconstructor:cache(unsigned cache_size, // cache size (in bytes)unsigned cache_associativity, // cache associativityunsigned cache_line_size, // cache block size (in bytes)Microprocessor Architecture1代写write_policy_t write_hit_policy, // write-back or write-throughwrite_policy_t write_miss_policy, // write-allocate or no-write-allocate unsigned cache_hit_time, // cache hit time (in clock cycles) unsigned cache_miss_penalty, // cache miss penalty (in clock cycles) unsigned address_width // number of bits in memory address);The simulator does not need to support fully associativeThe simulated cache should use the LRU replacementpolicy.The cache simulator should simulate cache read and write accesses. The trace files in the traces foldercontain the sequences of memory accesses that must be simulated. Each line of the trace files has the following syntax: r|w memory address where r and w represent read and write operations, respectively.For convenience, the parser is already included in the run function. The only modification to this function that is required is the insertion of invocations of the read and write functions.Microprocessor Architecture1代写In addition to the readand write functions, you must implement the following methods:print_configuration outputs the configuration of the cache simulator (cache size, associativity, cache line size, write hit and miss policies, cache hit time and miss penalty, and memory address width). An example output is shown below (please use the sameformat).

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