ECE463/563 – Microprocessor Architecture Project #2 Microprocessor Architecture代写 The goal of this project is to design and implement a C/C++ cycle-accurate simulator of a dynamicallyDue date: April 10, 2019Objective Microprocessor Architecture代写The goal of this project is to design and implement a C/C++ cycle-accurate simulator of a dynamically scheduled processor implementing the Tomasulo algorithm with Reorder Buffer.Students taking the course at the undergraduate level (ECE463) do not need to support store instructions (SW and SWS) in their simulator, while students taking the course at the graduate level (ECE563) will need to support store instructions as well.Code organization Microprocessor Architecture代写The project2_code.tar.gz archive contains C and C++ code templates for the simulator, as well as test cases to validate its operation. ECE563 students are required to use C++ code templates.In order to extract the code in a Linux environment, you can invoke the following command:tar –xzvf project2_code.tar.gzThis will create a project2_code folder containing two subfolders: c and c++, the former containing the C templates and the latter containing the C++ templates. The content of these two subfolders is very similar.Microprocessor Architecture代写The c and c++ folders have the following content:h/sim_ooo.cc (or sim_ooo.c): code templates for the dynamically scheduled processor’s simulator. These are the only files that you need to modify to implement the simulator.Test cases: test cases to validate the operation of the dynamically scheduled processor’s simulator. This folder contains five test cases. For each of them, you will find two files: Test caseN.cc and Test caseN.out. The former contains the test case implementation, and the latter the expected output of the test case. You should not modify any of the test case files. We recommend writing your own test cases to verify the functionality that is not covered by the test casesMakefile:Makefile to be used to compile the  The use of this Makefile will cause an object file (.o) to be created for each C or C++ file that is part of the project. If the compilation succeeds, the binaries corresponding to the test cases will be generated in the bin folder. You don’t need to modify the Makefile unless you are working on the floating-point pipeline simulator or you are using a library that is not included by default.asm: assembly files used by the testbin: once you compile the code, the test cases binaries will be saved into thisImportant Microprocessor Architecture代写The sim_ooo.h header file is commented and contains details on the functions/methods that you need to implement. Be sure to read the comments in this header file carefully before you start coding.Assumptions RequirementsData types and registers: The simulator operates on 32-bit integer numbers and 32-bit floating-point numbers stored in data memory. The simulator has 32 integer registers (R0-R31) and 32 single-precision floating- point registers (F0-F31).Memories: The instruction and data memories are separated. The instruction memory returns the instruction fetched within the clock cycle, while the data memory has a configurableExecution units and memory: The number of execution units and their latency must be configurable. The function init_exec_unit can be invoked at the beginning to configure the execution units used. Execution units can be of five kinds: INTEGER unit, floating-point ADDER, MULTIPLIER, DIVIDER and MEMORY (see exe_unit_t data type). The integer units are used for integer additions (and branches),subtractions and logic operations; the floating-point adders are for floating-point additions and subtractions; the multipliers are for integer and floating-point multiplications; and the dividers for integer and floating- point divisions. While the simulator can have multiple integer units, adders, multipliers and dividers, it will always have a single data memory unit (used by load and store instructions). While the processor can have multiple execution units of the same type with different latencies, in our test cases all the units of the same type will have the same latency. For simplicity, assume that all execution units are unpipelined. You can assume that the latency of the execution stage corresponds to that of the execution unit it Microprocessor Architecture代写Microprocessor Architecture代写4.Reservation stations and load buffers: Besides load buffers, the processor should have three kinds of reservation stations (see res_station_t data type). Integer reservation stations (INTEGER_RS) feed the integer units, add reservation stations (ADD_RS) feed the floating-point adders, and multiplier reservationstations (MULT_RS) are shared by multipliers and dividers. Load buffers (LOAD_B) are used by memory instructions.5.Initialization: the size of the data memory, the size of the reorder buffer, the number of reservation stations and load buffers, and the issue width can be configured when instantiating the simulator.Microprocessor Architecture代写/* Instantiates the simulatorNote: registers must be initialized to UNDEFINED value, and data memory to all 0xFF values*/sim_ooo(unsigned mem_size, // size of data memory (in byte) unsigned rob_size, // number of ROB entriesunsigned num_int_res_stations, // number of integer reservation stations unsigned num_add_res_stations, // number of ADD reservation stations unsigned num_mul_res_stations, // number of MULT/DIV reservation stations unsigned num_load_buffers, // number of LOAD buffersMicroprocessor Architecture代写unsigned issue_width=1 // issue width);Reservation stations, ROB, instruction window: the code template already contains data structures to model reservation stations, ROB and the instruction window. You can extend these data structures if you need, but you should not modify existingInstructionssupported: the processor simulator needs to support the following instructions (which are listed in the h header file).

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